The present invention relates to a clock selection circuit which, in response to selection data, selects and outputs one of a plurality of clock pulse signals having frequencies and/or phases different from each other.
Synchronous control systems such as microcomputers, disk controllers, etc. are required to switch a system clock pulse signal from one frequency and/or phase to another frequency and/or phase. For this purpose, a clock selection circuit is employed, which receives a plurality of clock pulse signals having frequencies and/or phases different from each other and selects and outputs one of them in response to selection data to switch the system clock pulse signal to the required frequency and/or phase.
However, the clock selection circuit according to prior art immediately switches the clock pulse signal to be selected in response to the change of the selection data. Since the clock pulse signals are asynchrous with each other, the leading edge or falling edge of the selected clock pulse signal happens to appear just after the change of the selection data. As a result, an unexpected excessive pulse of a very narrow pulse width is outputted as a system clock pulse. In other words, the system clock pulse signal temporarily takes a cycle period that is shorter than the cycle period of the clock pulse having the highest frequency. The systems are thereby brought into an erroneous operation.